1. Field of the Invention
This invention relates to methods of manufacturing semiconductor devices. Specifically, this invention relates to methods for reducing the mechanical stresses placed on semiconductor devices during manufacturing.
2. Discussion of Related Art
In the field of integrated circuit manufacture, the drive for increased performance and reduced cost leads to shrinking device dimensions and an increase in the density of semiconductor devices provided in a single chip. The reliability of semiconductor devices is dependent, in part, upon electrically isolating nearby semiconductor devices from one another. This increase in device density requires better and smaller insulation between active devices formed on a substrate.
One way of electrically isolating semiconductor devices from one another is by way of shallow trench isolation ("STI"). STI is typically formed by etching a shallow trench in the substrate between areas where active devices are to be formed, and thereafter typically filling the trenches with a dielectric material. The dielectric material acts as an insulator, electrically isolating active semiconductor devices formed on the remaining surface of the wafer. As the trenches are reduced in width, the width of the insulating material filling the trenches decreases. Nevertheless, the insulating capabilities of the dielectric material must remain high to maintain electrical isolation of adjacent devices. Unfortunately, as the width of the dielectric material narrows, the isolation can become less effective. This is due in part to the formation of defects within the dielectric layers which can result from mechanical and thermal stresses placed on the silicon and dielectric materials during STI manufacture.
Dielectric materials useful for STI include silicon oxides, such as tetraethylorthosilicate ("TEOS"), which can be deposited using a high temperature chemical vapor deposition (CVD) process in the presence of oxygen or ozone, a process herein termed "TEOS-O.sub.3 CVD". The deposited TEOS layer can then be densified by annealing at a high temperature, such as 750.degree. C. In general, however, TEOS-O.sub.3 CVD films treated in this fashion exhibit tensile stresses, which can lead to pinhole defects, and poor electrical isolation. Moreover, even if deposition conditions favor low stress films, the above annealing process can result in a stressed film.
One proposed solution to the problem of TEOS-O.sub.3 CVD stress is to perform the high-temperature annealing step at temperatures up to and including about 1200.degree. C. (Ishimaru et al., Mechanical Stress Induced MOSFET Punch-Through and Process Optimization for Deep Submicron TEOS-O.sub.3 Filled STI Device, Symposium on VLSI Technology Digest of Technical Papers:123-124 (1997); Damiano et al., Characterization and Elimination of Trench Dislocations, Symposium on VLSI Technology Digest of Technical Papers: 212-213 (1998); both reference incorporated herein in their entirety). The high-temperature annealing step can permit the realignment of misfits to form a more crystalline, denser structure, having less local stress and having better electrical isolating properties. Such high-temperature annealing processes can reduce the mechanical stress in the TEOS layer itself However, a STI TEOS-O.sub.3 CVD layer also suffers from defects due to the presence of mechanical stresses between the TEOS and the surrounding silicon substrate. The stresses result in the formation of defects between source and drain and pin-holes in the STI, which can lead to source-drain short-circuiting, trench--trench short circuiting, poor electrical isolation and unpredictable device function.
One theory which may account for the formation of stress within a dielectric layer is that rapid addition of new silicon dioxide moieties to the growing film can lead to mis-aligned molecules, herein termed "misfits." A new reactive moiety can attach to the surface of the growing film. However, new moieties may not be in alignment with the existing film structure, which can lead to gaps between the moieties in the film. If a deposition rate is relatively low, there is opportunity for the newly added moieties to move around at the surface, and they can become aligned with the crystal structure of the film. Re-alignment can thereby decrease the number of gaps between moieties in the film. Further addition of new moieties can result in a similar attachment/realignment process thereby resulting in a dense, uniform film structure having good electrical isolation properties. However, with deposition rates sufficiently high, there can be less opportunity for newly attached moieties to re-align to the existing film structure. Upon attachment of additional moieties, the mis-aligned moieties can become trapped within the film.
With rapid deposition of moieties onto a film surface, the film can exhibit a compressive stress. A compressive stress is characterized by a tendency of atoms and molecules in the film to expand laterally in a direction parallel to the film surface. According to this theory, the formation of compressive stress can lead to a tendency for the film to buckle, a process which can lead to the formation of gaps in the film. When deposited in a shallow trench, a compressive or tensile film can lead to small scale stresses within the trench, termed "local stresses." Although this is one theory which could account for the poorer electrical isolation of stressed TEOS films, still other theories may account for the observations.
In addition to local stresses within shallow trenches, stresses can be created between different areas of a wafer. A compressive film in a shallow trench exerts a force against the walls of the trench, tending to expand the trench in an outward, or lateral direction. Compressive stress within the trench tends to expand the surface of the wafer in a direction parallel to the surface, which tends to warp the wafer. This type of larger scale stress is herein termed "global stress."
Another approach to reducing global stresses on a semiconductor wafer has been the filling the trench with TEOS-O.sub.3 CVD oxide followed by a cap layer of high-density plasma CVD (HDPCVD) oxide. (Park et al. Stress Minimization in Deep Sub-Micron Full CMOS Devices by Using an Optimized Combination of the Trench Filling CVD Oxides: IEEE 1997:27.4.1 (1997), incorporated herein fully by reference). A HDPCVD oxide layer, can produce a film having compressive stress. According to the above theory, by providing a layer of film having compressive stress on the top of a TEOS-O.sub.3 CVD layer having tensile stress, the global stress on the wafer can be reduced.
An example of this prior art approach to decreasing global stress is shown in FIG. 1. FIG. 1 shows a shallow trench in a silicon substrate which has filled with oxide according to the prior art. Device 100 comprises silicon substrate 104 within which two shallow trenches are shown. A layer of nitride 108 is depicted on the surface of the silicon substrate 104. A layer of first TEOS-O.sub.3 CVD oxide 112 is shown filling substantially all of the gap in the shallow trench. A layer of HDPCVD oxide 116 is shown on the top of the first oxide layer 108. Note that the layer of HDPCVD oxide does not extend below the surface of the silicon substrate, does not extend within the shallow trench, and therefore cannot reduce the local stress within the shallow trench.
However, neither of the above processes adequately address the problems of mechanical stress deep within the shallow trenches themselves, and therefore do not minimize the overall stress on the semiconductor wafer after subsequent processing. The presence of continued stress in the shallow trenches can result in the formation of defects in the dielectric material during subsequent processing steps, leading to loss of electrical isolation and device failure.
Therefore, one object of this invention is the development of methods for producing STI with minimized mechanical stresses within the shallow trench.
Another object of this invention is the development of methods for producing STI with improved electrical insulating properties.
A further object of this invention is the development of methods for the production of semiconductor devices with high reliability.
A yet further object of this invention is the manufacture of semiconductor devices having improved electrical properties.
Another object of this invention is the manufacture of semiconductor devices with reduced mechanical stresses being introduced into STI during manufacture.
An further object of this invention is the manufacture of semiconductor devices having increased useful lifetimes.